The present invention relates to a programmable logic array circuit.
Programmable logic arrays (PLAs) and field programmable logic arrays (FPLAs) are well known in the art. PLAs are programmed during their manufacture, while FPLAs can be programmed away from the place where they are manufactured. Typically, FPLAs comprise an array of logical AND gates and an array of logical OR gates which can be programmed for a specific function. Each output function is the sum (logical OR) of selective products, where each product is the product (logical AND) of selected inputs. The FPLAs can be programmed so that any input line can be connected to any AND gate input and any of the products (results of the ANDs) can be summed by any of the OR gates. One way the FPLA can be programmed is by blowing or not blowing a fusable link coupling an input to a logical AND gate or an AND gate output to a logical OR gate.
Programmable array logic circuits (PALs) are also well known in the art. In general, these devices comprise a plurality of field programmable AND gate arrays connected non-programmably to specific OR gates. (See, for example, U.S. Pat. No. 4,124,899.)
The gates on the logic array circuits are formed by having inputs which can be coupled to a plurality of term lines. This coupling is typically achieved through a transistor connection such that an input line can force the term line, through the transistor, to a low voltage level. The term line itself thus acts as the output of the gate, with it being at a high level only if none of the inputs are causing a transistor to pull it to a low level (NOR gate). Other mechanisms are possible for coupling an input line to a term line to result in a NAND gate configuration rather than a NOR gate configuration.
One disadvantage of FPLAs and PAL circuits are that the output of the logical arrays is always a function of the result of specified AND gates followed by OR gates. Thus, a single level Boolean logic circuit output (only AND or only OR) is not available.
The PLAs incorporate two programmable array planes in order to give the combination of random AND functions and random OR functions. Because a signal must propagate through both of these planes, these circuits have a long propagation time. The PAL circuits have a rigid configuration in which product terms are wasted in some applications since they are not used. The fixed requirement of AND gates feeding OR gates means that random logic is not possible and thus a schematic type entry cannot be achieved unless the schematic is specifically designed to be built of AND/OR combination building blocks. The rigid configuration of these circuits results in an inefficient use of the terms.